The IBM z16 platform introduces an innovative industry leading processor cache architecture that extends the value of prior generations of hardware within a new single chip, single cache design. This presentation will cover the motivations driving the shift from the prior generations tiered inclusive cache design to private-shared clusters of caches, the underlying performance implications, and the implications in interpreting CPUMF data.

Speaker(s): Bradley Snyder (IT Specialist); Craig R Walters (STSM, System z Hardware Performance Lead, IBM Master Inventor)